🔲 AI,GPU IC, SOC IC - dane8036 · Scour

Microchip empowers real-time edge AI

edn.com·1h

AI in Multiple GPUs: Understanding the Host and Device Paradigm

towardsdatascience.com·10h

🧮Tensor Cores

Powering AI Centers with AI Spines

blogs.arista.com·1h

AI Inference Needs A Mix-And-Match Memory Strategy

semiengineering.com·15h

AI Startups and GPUs

news.ycombinator.com·2d·

Discuss: Hacker News

Nvidia DGX Spark update cuts idle power by 32% or more — hot-plug detection on ConnectX NIC makes for a more efficient AI workstation

tomshardware.com

·3h

🔲System on chip

arxiv.org·18h

🧮Tensor Cores

harishsg993010/tiny-NPU: opensource NPU for LLM inference (this run gpt2)

github.com·3h·

Discuss: r/LocalLLaMA

Cisco unveils new AI networking chip, taking on Broadcom and Nvidia

finance.yahoo.com·23h

💎ASIC Design

Can You Self-Host an Efficient AI at Home or for your Company?

dev.to·4h·

Discuss: DEV

AI agent automates front-end chip workflows

edn.com·1h

🤖Agentic Engineering

OpenAI sidesteps Nvidia with unusually fast coding model on plate-sized chips

arstechnica.com·25m

Code, Compute and Connection: Inside the Inaugural NVIDIA AI Day São Paulo

blogs.nvidia.com·1h

Why CPUs sit at the center of AI infrastructure: Five takeaways from Futurum’s latest report

newsroom.arm.com·3h

Olix is pitching a new way to do AI chips

fudzilla.com·1d

💎ASIC Design

Porting an INT8 VHDL CNN from Intel Agilex 3 to Lattice Certus-NX

news.ycombinator.com·10h·

Discuss: Hacker News

The Facade of AI Safety Will Crumble

lesswrong.com·7h

A C implementation of the inference pipeline for the Mistral AI’s Voxtral Realtime 4B model

blog.adafruit.com·6h

🧮Tensor Cores

Building an x86 "Motherboard" and Running MS-DOS on It (ikejima.org)

blog.ikejima.org·13h·

Discuss: r/hardware

🔲System on chip

Giving AI Agents Access to a Compiled Design and Verification Database

semiwiki.com·7h

🤖Agentic Engineering

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